The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, resulting in several problems.
One such problem is the difficulty in applying stress effectively for high-density devices. Effectively applying stress is limited by several factors, such as smaller gate-to-gate spacing, less source/drain volume, and raised source/drain structures. Traditional contact etch stop layer (CESL) stressor and stress memorization techniques need a stress liner surrounding the gate stack and the spacer. However, these techniques are less effective because the smaller gate-to-gate space impedes insertion of the stress liner. Further, for raised source/drain regions, the stress liner is farther away from the channel and less stress can be transferred to the channel. Additionally, gate stack aspect ratios are usually higher at the advanced technology node, which prevents stress from transferring to the channel.
Another known stress technique, embedding in the source/drain regions either silicon germanium (eSiGe) for pMOSFETS or silicon carbide (eSiC) for nMOSFETS, is ineffective as the source/drain volume is reduced with scaling to smaller and smaller pitches. Such techniques are particularly ineffective for semiconductor devices with extremely thin silicon-on-insulator (ETSOI) substrates (employed for the fundamentally superior short channel control characteristics).
A need therefore exists for methodology enabling fabrication of semiconductor devices with improved channel stress, and the resulting devices.